1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device which forms semiconductor elements in an active element separation region (hereinafter referred to as “active region”) on a semiconductor substrate.
2. Description of the Related Art
With recent progress in integration density and functions of semiconductor devices, there is a demand for smaller element separation regions for isolating many (or more) semiconductor elements such as MOS transistors. A shallow trench isolation (hereinafter referred to as “STI”) process is drawing an attention as an effective technology for providing fine element isolation (separation) regions.
The STI process is a technique that forms a groove (hereinafter referred to as “trench”) on a semiconductor substrate by etching and fills the trench with an insulating material so as to separate (isolate) semiconductor elements from each other. This can decrease dimensional variations (deviations) from design (desired) dimensions of the element. Thus, the STI process is theoretically best suited for provision of fine element separation (isolation) regions. Further, the STI process has an advantage in that, after filling the trench with the insulating material, the substrate is processed by etching-back and/or chemical mechanical polishing (hereinafter referred to as “CMP”) so as to have improved surface planarity (smoothness) sufficient to conduct a high precision lithographic process. Moreover, the formed trench is not only useful for the element separation but may also be used as an alignment mark for high precision positioning in a photolithographic process. In this case, an oxide film in the trench is used as the alignment mark and this oxide film must be removed by etching after the CMP process so as to maintain an alignment light at a sufficient optical waveform intensity. The alignment light is radiated on the substrate from a certain light source.
FIGS. 1A to 1D of the accompanying drawings show a conventional method for manufacturing a semiconductor device, and in particular, a process for element separation (isolation) and formation of an alignment mark using the STI process.
In a process of filling a trench shown in FIG. 1A, a pad oxide film 102 and a silicon nitride film 103 are formed in this order on a surface of a silicon substrate 101. Then, a plurality of trenches 110 and 120 are formed by photolithography and/or etching for element separation and alignment marks, respectively. Following this, the trenches 110 and 120 are filled with another oxide film 105.
In an ACW photolithography/etching process shown in FIG. 1B, the oxide film 105 formed in an active region 130 except the element separation (isolation) trenches 110 is removed by photolithography and etching. This process is carried out in order to prevent the oxide film 105 from remaining on a wide area even after a next process (i.e., STI-CMP process). ACW stands for an “active window.”
In an STI-CMP process shown in FIG. 1C, the silicon substrate 101 on which some oxide film 105 remains is subjected to planarization using a CMP process. As a result of this process, the oxide film 105 remains only in the trenches 110 and 120.
In an AM photolithography/etching process shown in FIG. 1D, the oxide film 105 filled in the alignment mark trench 120 is eliminated by photolithography and etching processes. “AM” means an alignment mark. This process is necessary for the following reason. If a photolithographic process is applied to a semiconductor device having a film exhibiting high absorption of alignment light (e.g., polysilicon film), an alignment mark has an insufficient step height difference (trench depth), thus not having desired alignment waveform intensity. If the alignment waveform intensity is not sufficient, alignment precision is deteriorated and, sometimes an alignment process cannot be conducted.
On the other hand, the AM photolithography/etching process increases a production cost. In order to omit the AM photolithography/etching process, there have been some proposals. For example, Japanese Patent Application Kokai (Laid-Open) No. 2002-134701 discloses that an insulation film filled in a region, on which a large active region is formed, and a part of the insulation film filled in another region, on which an alignment mark is formed, are simultaneously eliminated by photolithography and etching (see FIG. 1C and paragraphs 0022 to 0024, and FIG. 4A and paragraphs 0034 to 0035 in the Japanese publication). Japanese Patent Application Kokai No. 2001-102440 discloses that a process of etching a separation oxide film from an alignment mark trench is performed with the same mask as that used in a process of forming a wall and/or in a process of forming a resist pattern employed for ion implantation for threshold value adjustment. Japanese Patent Application Kokai No. 2002-50682 discloses that a silicon oxide film formed in a large active region and another silicon oxide film formed in an alignment pattern trench are removed simultaneously (see FIG. 1(2) and paragraphs 0021 to 0022 in the Japanese publication).